Graphics subsystem bypass method and apparatus

ABSTRACT

The present invention provides an on-screen graphics (OSD) subsystem for overlaying OSD graphic images onto analog or digital video source signals. The OSD system has a video graphics bypass path and graphics bypass switch for directing an analog video channel around the OSD subsystem during time intervals when the OSD subsystem is not required to insert graphics into the source signal.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application is a continuation of PCT InternationalApplication No. PCT/US99/22305, filed Sep. 27, 1999, which applicationis incorporated herein by reference.

BACKGROUND

[0002] The present invention relates to cable television (CATV) systems.More particularly, the present invention pertains to a method andapparatus for bypassing a digital on-screen display graphics insertionsubsystem.

[0003] The wide spread use of analog video displays has created a needfor displaying graphic images such as alphanumeric characters or othergraphics along with analog video data. The graphics are typically laidover a video signal received from a separate remote source such as abroadcast television transmission, a video disk, a video tape or anyother video source. Various arrangements are known for overlayinggraphic images over a video signal received from such a separate remotevideo source.

[0004] U.S. Pat. No. 5,051,817 to Takano discloses a system forsuperimposing color characters on an input video signal. In this system,a first sync separator separates horizontal sync pulses from the inputvideo signal. These horizontal sync pulses are used by a phase lock loop(PLL) circuit to generate a reference clock signal (P1) that is lockedto the horizontal sync pulses of the input video signal. A second syncseparator, a timing generator, a burst gate, and a second PLL circuitgenerate an oscillation output signal that is phase locked to a burstsignal of the input video signal. The reference clock signal and theoscillation output signal are used to synchronize a generated charactersignal with the input video signal. A changeover signal generatorgenerates changeover control signals to output only the input videosignal, or the input video signal superimposed with color characters.

[0005] U.S. Pat. No. 5,541,666 to Zeidler et al. discloses a system foroverlaying digital character signals on an analog source signalincluding a predetermined color sub-carrier which includes a sub-carrierphase locked loop, a digital character generating device, a digitalvideo encoder and a switching device. The subscriber phase locked loopseparately generates a color sub-carrier and a system clock signal whichare locked to the color sub-carrier of the analog video source system.The digital character generating device detects horizontal and verticaltiming of pixel information in the analog video source signal, andgenerates digital character signals that are to be overlaid inpredetermined pixels of the analog video source signal. The digitalvideo encoder is responsive to the color sub-carrier and system clocksignals for generating a separate color sub-carrier which is locked tothe color sub-carrier of the analog video source signal. The digitalvideo encoder also converts the digital character signals from thedigital character generating means into an analog video output signalthat includes the color sub-carrier generated in the digital videoencoder. The switching means directs the analog video output signal fromthe digital video encoder or the analog video source signal to an outputof this system during times when the digital character is to be overlaidor not overlaid respectively on the analog video source signal.

[0006] A problem exists with these techniques in that insertion ofdigital information into an analog video source may only be required incertain time intervals. The insertion process inherently degrades thevideo signal. Signal degradation occurs both during time intervals whendigital information is inserted and during time intervals when there isno digital information presented for insertion.

SUMMARY

[0007] It is therefore an object of the present invention to provide amethod and apparatus for overlaying graphics on video signals and tobypass an OSD graphics subsystem for overlaying the graphics on thevideo signals during intervals when there are no graphics are presentedfor overlaying.

[0008] These and other objects have been achieved by providing agraphics subsystem for receiving digital video source signals orconverting analog video source signals to digital video signals,inserting on screen display (OSD) graphics into the video source signalsto form a composite digital signal and converting the composite digitalsignal to an analog video signal for output to a display. A graphicssubsystem bypass circuit is provided for passing inbound analog videosource signals directly to the display during intervals when no OSDgraphics are present for overlaying.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The invention will now be described by way of example withreference to the accompanying figures of which:

[0010]FIG. 1 is a block diagram of a system containing a graphicssubsystem bypass according to the present invention.

[0011]FIG. 2 is a flow diagram for the operation of the system in FIG.1.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0012]FIG. 1 is a block diagram of a settop terminal 10. The settopterminal 10 contains a tuner 12 coupled to a cable input from acommunity antenna television (CATV) network. A switch 14 is coupled tothe output of the tuner 12. It should be understood by those reasonablyskilled in the art that the switch 14 may optionally be replaced by asplitter. Outputs 15, 17 of the switch 14 are coupled to an analog videopath 19 and a digital video path 21 respectively. An analog channelvideo demodulator 16 is coupled to the first switch output 15 along theanalog video path 19. It should be understood by those reasonablyskilled in the art that the analog channel video demodulator 16 may alsooptionally include a descrambler in systems where the cable input is ascrambled signal.

[0013] A digital channel demodulator 18 is coupled to the second switchoutput 17 along the digital video path 21. It should be understood bythose reasonably skilled in the art that the digital channel demodulator18 may optionally include a decryptor for use in systems havingencrypted digital information being passing through the tuner 12. Amotion picture expert group (MPEG) decoder 20 is coupled to the outputof the digital channel demodulator 18 within the digital video path 21.Both the analog video and digital video paths 19, 21 are coupled to anon-screen display (OSD) graphics subsystem 40.

[0014] The OSD graphics subsystem 40 includes an analog to digital (A/D)convertor 42 coupled to the analog video path 19 and a switch 43 havingtwo inputs 45,47. The inputs 45,47 are coupled to the A/D convertor 42and the MPEG decoder 20 respectively. Also included in the OSD graphicssubsystem 40 is an OSD insertion unit 44 coupled to switch output 49, adigital to analog (D/A) convertor 46, which is coupled to the OSDinsertion unit 44 and an output 50. The OSD graphics subsystem 40including the A/D convertor 42, the switch 43, the OSD insertion unit 44and the D/A convertor 46 may comprise a single chip or chip set, forexample ATI Technologies Rage Pro and Rage Theatre. It should berecognized that other vendors offer similar chips or chip sets havingthese functions. Any such suitable chip or chip set having thesefunctions could be utilized.

[0015] A graphics bypass switch 24, having two inputs 56, 54, is coupledto the OSD graphics subsystem output 50 and to an OSD bypass path 22.The bypass path 22 extends from the analog video path 19 to the graphicsbypass switch input 54. A video output 60 is provided from the graphicsbypass switch output 58. Memory 52 is coupled to the OSD graphicssubsystem 40. Additionally, microprocessor 26 is provided forselectively controlling each of the components described above.

[0016] Referring to FIG. 2, general operation of the system 10 of FIG. 1will now be described. First, an input channel from the tuner 12 issplit or switched. Next, a determination is made by the microprocessor26 whether the channel is digital or analog. If it is a digital channel,demodulation and an MPEG decoding process is initiated throughmicroprocessor control of switch 14 followed by an on-screen displayinsertion process to insert the OSD information into the digital videoinput. Following the OSD insertion process a video signal containingboth digital video and graphics inserted information is converted toanalog at the digital to analog convertor 46 and output to a standardmonitor. Returning to the top of FIG. 2, if the channel is analog it isdirected along the analog path 19 through microprocessor control ofswitch 14. It is passed then through the OSD graphics subsystem, or abypass is activated by the microprocessor 26 to redirect the demodulatedinput channel directly to the video output 60 for display on a standardmonitor.

[0017] System operation will now be described in greater detail withreference to FIG. 1. The memory 52 contains OSD graphics imageinformation in digital format which is stored there by themicroprocessor 26. It should be understood, that this information may bemodified by the microprocessor 26 in order to display different OSDgraphics images on the video output 60. The settop terminal 10 receivesa cable input from a CATV network via the tuner 12, which selects adesired channel from the cable input. Based upon whether the selectedchannel is digital or analog, the switch 14 directs the selected channelto the analog channel video demodulator 16 through the analog video path19 or to a digital channel demodulator 18 through the digital video path21. These will be referred to as the digital channel and the analogchannel. The digital channel typically contains MPEG compressed video,while the analog channel typically contains picture signals such as NTSCor PAL or other standard signals. It should be understood however thateach of these channels may carry other information content in the formof analog and digital signals.

[0018] The analog channel video demodulator 16 serves to demodulate theanalog channel and also optionally serves to descramble any scrambledanalog video signal. A demodulated analog video signal is fed from theanalog channel video demodulator 16 along the analog video path 19 toboth the graphics bypass path 22 and the OSD graphics subsystem 40.

[0019] The digital channel demodulator 18 serves to demodulate thedigital channel and may optionally de-encrypt any digitally encryptedsignal. A demodulated digital signal is fed from the digital channeldemodulator 18 along the digital video path 21 to the MPEG decoder 20.It should be understood that while the decoder 20 is shown as an MPEGdecoder, other digital compression techniques may be utilized anddecoded accordingly. The MPEG decoder 20 serves to decode the MPEGencoded signal into a pure digital video signal, which is fed into theOSD graphics subsystem 40.

[0020] The digital video signal coming from the MPEG decoder 20 is fedto the second switch input 47. The switch 43 is operated by themicroprocessor 26 to feed the A/D converted video signal to the OSDinsertion unit 44 during selected time intervals when the tuner 12 istuned to an analog channel. The switch 43 is also operated by themicroprocessor 26 to feed the digital video signal coming from the MPEGdecoder 20 to the OSD insertion unit 44 during other selected timeintervals when the tuner 12 is tuned to a digital channel. Dependingupon the switch's position, the OSD insertion unit 44 combines thedigital video signal from the digital video path 21 or the digitizedanalog video signal from the analog video path 19 with the desired OSDgraphics previously stored in memory 52. The combined or compositesignal is then fed to the D/A convertor 46 for conversion to an analogsignal, which contains digital or analog video source signals from thetuner 12 and OSD graphics inserted from memory 52. The memory 52 alsoserves to temporarily store A/D information, D/A information and datafor the OSD insertion unit 44.

[0021] The graphics bypass switch 24 is controlled by the microprocessor26 to switch the video output 60 between the graphics bypass path 22 andthe OSD graphics subsystem output 50. It should be appreciated that theOSD graphics subsystem, by use of A/D and D/A convertors 42, 46,degrades the signal quality at the video output 60. Therefore, whenthere is no OSD graphics present for combination with the analogchannel, the bypass path 22 serves to pass the analog video signaldirectly to the video output 60 without any degradation that wouldotherwise be experienced through the OSD graphics subsystem 40.

[0022] An advantage of the present invention is that during intervalswhen OSD graphics is not required for combination with an analog signal,the analog video signal may be passed directly to a video output 60without degradation experienced through signal conversions in the OSDgraphics subsystem 40.

What is claimed is:
 1. A video graphics subsystem for use in a videoterminal comprising: a digital video input configured to receive adigital signal; an analog video input configured to receive an analogvideo signal; an analog to digital converter having a digital output andan input for receiving the analog video signal from the analog videoinput; an on-screen display insertion unit having a digital output andan input selectively coupled to both the digital video input or thedigital output of the analog to digital converter; a digital to analogconverter having an analog output and a digital input coupled to thedigital output of the on-screen display unit; and a bypass extendingfrom the analog video input through a switch connected to the analogoutput, wherein said analog video signal bypasses said analog to digitalconverter the on-screen display, and the digital to analog converterwhen no digital signal is received.
 2. The video graphics subsystemrecited in claim 1 further comprising a second switch having inputs eachcoupled to the digital video input and the analog video input and anoutput coupled to the on-screen display insertion unit input.
 3. Thevideo graphics subsystem recited in claim 1 further comprising a memoryfor storing information from the analog to digital and digital to analogconvertors.
 4. The video graphics subsystem recited in claim 3 furthercomprising a microprocessor for generating and storing a graphic in thememory.
 5. The video graphics subsystem recited in claim 4 wherein theon-screen display insertion unit receives the graphic and combines thegraphic with a signal applied to its input.
 6. The video graphicssubsystem recited in claim 5 wherein the microprocessor directs a signalon the analog video input to the bypass during intervals when no graphicis required.
 7. A video graphics subsystem comprising: a firstconverting means for converting an inbound analog video signal to adigital video signal when a digital graphic is present; insertion meansfor combining the digital video signal with the digital graphic to forma composite digital video signal; a second converting means forconverting the composite digital video signal to a composite analogvideo signal; and bypass means for bypassing the first converting means,the insertion means and the second converting means when said digitalgraphic is not present.
 8. The video graphics subsystem recited in claim7 wherein the bypass means comprises a bypass switch.
 9. The videographics subsystem recited in claim 8 wherein the bypass switch iscontrollable in response to sensing the requirement of a digitalgraphic.
 10. The video graphics subsystem recited in claim 9 furthercomprising a microprocessor for sensing the requirement of a digitalgraphic and controlling the switch.
 11. A method for insertingintermittent graphics signals into an analog video signal comprising thesteps of: a) converting the analog video signal to a digital videosignal; b) inserting at least one of the intermittent graphics signalsinto the digital video signal forming a composite digital video signal;c) converting the composite digital video signal to a composite analogvideo signal; and d) bypassing steps a, b, and c during time intervalswhen the intermittent graphics signals are not present, whereby saidanalog video signal is output.
 12. The method of claim 11 furthercomprising the step of generating a digital representation of an imageto form the graphics signals.
 13. The method of claim 12 furthercomprising the step of storing the digital representation in a memory.14. The method of claim 13 further comprising the step of reading thedigital representation from the memory prior to step b.
 15. A videographics subsystem having on-screen display insertion means forconverting a video signal from an analog source signal to a digitalsignal, combining graphics information with the digital signal to form acomposite signal, and converting the composite digital signal to ananalog video output signal coupled to a display, the subsystem beingcharacterized by: a bypass having a controllable switch for coupling theanalog source signal directly to the display when no graphicsinformation is present.
 16. The video graphics subsystem recited inclaim 15 wherein the bypass comprises a switch.
 17. The video graphicssubsystem recited in claim 15 wherein the switch is controlled by amicroprocessor such that the bypass is deactivated during intervals whengraphics information is desired and the bypass is activated duringintervals when graphics information is not desired.
 18. The videographics subsystem recited in claim 15 further comprising a memory forstoring the graphics information.
 19. The video graphics subsystemrecited in claim 18 further comprising a microprocessor for generatingand storing the graphics information in the memory.